Conventional memory devices include a class of memory devices referred to as static random access memory (SRAM) devices. As illustrated by FIG. 1, a conventional SRAM device 100 includes a plurality of column units 101 arranged side-by-side in a semiconductor substrate. Each of the column units 101 is illustrated as including a column of SRAM cells 107, a bit line precharging and equalization circuit 109, which is responsive to an active low bit line precharge signal /PBL, and a bit line selection circuit 111, which is responsive to a pair of column selection signals Y and /Y. The column of SRAM cells 107 is electrically coupled to a corresponding pair of bit lines (BL and /BL) and each SRAM cell within the column 107 is responsive to a corresponding word line signal (SWL1–SWLn). The bit line precharging and equalization circuit 109 includes PMOS transistors P1–P3 and the bit line selection circuit 111 includes transmission gates TG1 and TG2. As will be understood by those skilled in the art, setting the bit line precharge signal /PBL low during a precharge time interval causes both bit lines BL and /BL to be equalized at a logic 1 voltage level (e.g., Vdd). In addition, setting the bit line precharge signal /PBL high and the true column selection signal Y high (and /Y low) will cause the pair of bit lines BL and /BL to be connected to a pair of data lines DL and /DL. During a read operation, these data lines DL and /DL provide read data to a sense amplifier 103 and a data output buffer 113 within a read path of the memory device. During a write operation, the data lines DL and /DL receive write data from a write driver 105, which is electrically coupled to a data input buffer 115.
As illustrated by the timing diagram of FIG. 2, a leading edge of a clock signal CLK (for a synchronous SRAM device) or an address ADD (for an asynchronous SRAM device) may result in the switching of the word line, column selection and bit line precharge signals illustrated by FIG. 1. In particular, prior to receipt of a leading edge of the clock signal CLK (or address ADD), the bit line precharge signal /PBL is held low and the pair of bit lines BL and /BL are held high at logic 1 voltage levels. Then, upon receipt of the leading edge, the bit line precharge signal /PBL is switched high to an inactive level, a selected word line SWL1 is switched high to activate a row of SRAM cells and the column selection signals Y and /Y are set high and low, respectively, to thereby electrically couple the pair of bit lines BL and /BL to the corresponding pair of data lines DL and /DL. These switching operations result in a transfer of differential read data from a selected memory cell to the corresponding bit lines BL and /BL and then to the corresponding data lines DL and /DL. This differential read data is then detected and amplified by the sense amplifier 103 and output to the data output buffer 113.
A possible layout of the SRAM device 100 of FIG. 1 is illustrated by FIG. 3. In particular, FIG. 3 illustrates an SRAM device having a capacity of 16K bits by 16K bits, with each sub-block of 1K bits by 2K bits worth of memory being arranged as 2048 rows of SRAM cells extending in a horizontal word line direction by 1024 columns of SRAM cells extending in a vertical bit line direction. Each sub-block is associated with a corresponding bit line control circuit and peripheral circuit. Unfortunately, the bit line capacitance associated with each pair of bit lines (BL and /BL), which span 2048 rows of SRAM cells, may be excessive and thereby increase active power (i.e., switching power) and access time during reading and writing operations.
To address these problems of excessive active power and access time, integrated circuit memory devices may utilize hierarchical bit line selection circuits that reduce bit line capacitance. In some of these memory devices, two or more SRAM cells may be used in combination to divide a bit line into two or more sub bit-lines, which are combined to form two or more levels of hierarchy. One such memory device is disclosed in an article by A. Karandikar et al., entitled “Low Power SRAM Design Using Hierarchical Divided Bit-Line Approach,” ICCD Proceedings, pp. 82–88, October 1998. In particular, the Karandikar et al. article illustrates how the drain capacitance loading on a bit line can be reduced by reducing the number of access transistors connected to the bit line by a factor of four or more. However, this advantageous reduction in bit line capacitance typically incurs a layout area penalty because additional column decoding and related circuits are required to control the additional access transistors at the multiple levels of hierarchy. U.S. Pat. No. 5,715,189 to Asakura also discloses a memory device having a hierarchical bit line arrangement.
Conventional techniques to achieve reductions in layout area of SRAM memory devices are disclosed in an article by S. M. Jung et al., entitled “The Revolutionary and Truly 3-Dimensional 25F2 SRAM Technology with the Smallest S3 (Stacked Single-Crystal Si) Cell, 0.16 um2, and SSTFT (Stacked Single-crystal Thin Film Transistor) for Ultra High Density SRAM,” Symposium on VLSI Technology Digest, pp. 228–229, June 2004, the disclosure of which is hereby incorporated herein by reference. In this article, an SRAM cell having a reduced cell size is described as having two thin-film PMOS load transistors and two thin-film NMOS pass transistors stacked over two planar NMOS pull-down transistors. In particular, FIG. 3 of this article shows a 6T SRAM cell having a pair of NMOS bulk transistors, a pair of PMOS load transistors on an interlayer dielectric layer (ILD1) and a pair of NMOS access transistors on another interlayer dielectric layer (ILD2).